1. Technical Field
The present invention relates in general to attaching memory mapped devices to a multilevel bus hierarchy and in particular to allowing memory mapped devices to be attached to any level of a multilevel bus hierarchy. Still more particularly, the present invention relates to forwarding memory mapped commands to lower levels of a multilevel bus hierarchy without precluding attachment of memory mapped devices to higher levels of the bus hierarchy.
2. Description of the Related Art
Memory mapped devices in a data processing system use a portion of the date processing system's total memory address space for their input/output (I/O) address space rather than using a dedicated I/O address space. As is known in the art, use of memory mapped devices avoids the requirement of extra signals to identify or select devices and allows all processor instructions, rather than merely a limited set, to be used in conjunction with the device.
A common problem for data processing systems using memory mapped devices is the potential for decoding conflicts by multiple devices. Many data processing systems attach several memory mapped devices to secondary or tertiary buses attached to the system bus through a system memory controller. The system memory controller normally acknowledges all memory addresses and passes operations with memory addresses which it does not actually control to the buses below it. If the buses below do not accept the operation passed by the system memory controller, some error condition is asserted to the processor(s) on the system bus.
The method described above works if the bus hierarchy contains no memory mapped devices or buses above or at the same hierarchy level as the system memory controller. If additional devices are added to the bus hierarchy at or above the level of the system memory controller, addresses for these devices cannot be acknowledged by the system memory controller.
It would be desirable, in a system including secondary or tertiary buses attached to a system memory controller, to allow operations with memory addresses for devices on the secondary or tertiary buses to be passed below the system memory controller while allowing additional devices or buses to be attached to the system bus at a level equal to or above the system memory controller in the bus hierarchy. It would further be desirable to dynamically forward memory mapped commands to the appropriate memory mapped devices anywhere in the bus hierarchy.
It would also be desirable to allow the addition, at a later time or in other configuration, of other devices at or above the bus level of the I/O bridge connecting the secondary bus with the system bus without requiring either changes to the system memory controller hardware (adding decoding range registers or look up tables, etc.) to permit such later additions or other configurations or different programming of the system memory controller for different configurations.